Integrated circuits are formed on a semiconductor substrate, such as silicon, silicon-germainium or gallium arsenide, by patterning films of various materials on the substrate. These patterns of films may be made of conductors or insulators such that complex electrical circuits are formed. Also, the films and the patterns in the films may be of different materials, which is essential for transistor and diode fabrication. During the processing of one substrate, millions of individual devices, which could constitute hundreds of individual "chips," may be formed.
In order for each of the chips to function properly, it is essential that the desired pattern of the circuit design be properly replicated onto the substrate film. If there is a failure in the processing such that the pattern is not properly applied to the substrate for any of the devices, then it is possible that the entire chip will not function and will need to be discarded.
As the size of the devices and the separation between the devices decrease, more devices can be placed on a chip. The complexity of manufacturing the chip increases with a decrease in size and separation, however, and the tolerances for errors in processing dramatically decrease. To manufacture the layers of film without errors or defects, it is essential that the semiconductor wafer be flat or "planar." Failure of the wafer to achieve flatness at any layer of material can cause errors at subsequently deposited levels.
The unit process operation used to ensure that the wafer is planar is chemical mechanical planarization. The chemical mechanical planarization process involves holding the semiconductor wafer against a rotating polishing pad surface at a controlled pressure. A polishing slurry that has an abrasive particle (such as alumina, silica, ceria, or zirconia) and has chemical etchants is flowed onto the pad to aid in the removal of material. Because of the rotating nature of the process and manner in which the wafer is pressed against the polishing pad, the material on the wafer that is furthest from the substrate is polished at the fastest rate while the material that is recessed is not polished at all. Thus, areas of the wafer surface that are protruding off the substrate the most are polished back to the recessed areas resulting in a finished, "planarized," flat surface.
One of the ways in which chemical mechanical planarization is used is in metallization, or formation of the network of conducting wires that create the circuit. In this step, the objective is to create a pattern of wires of tungsten, aluminum, or copper that are separated by dielectric all within the same level of the chip. The method that is used, which is often referred to as damascene metallization, starts by uniformly depositing a conformal film of the dielectric, which is generally silicon dioxide (SiO.sub.2), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). The dielectric film is then patterned such that both trenches and holes are etched into the dielectric. Next, a thin layer (usually 10 to 100 nanometers (nm) thick) of liner material, such as titanium (Ti) and titanium nitride (TiN) or tantalum (Ta) and tantalum nitride (TaN), is deposited by physical vapor deposition (PVD), otherwise known as sputter deposition, or chemical vapor deposition (CVD). Finally, approximately 600 to 1,000 nm of the conductor, which is generally tungsten (W), copper (Cu), or aluminum (Al), is deposited so that the remainder of the trenches and holes are filled.
To isolate the individual conductor-filled trenches and holes from each other electrically, it is necessary to remove the excess conductor that is not in the trenches or holes. Although it is possible in principle to remove this metal by a chemical etch or a plasma reactive ion etch process, these processes are unacceptable because they tend to remove the conductor at nearly the same rate at the top of the trenches as in the trenches. Because it planarizes as it removes material, however, chemical mechanical planarization is exceedingly efficient at removing the excess metal.
The typical scheme to isolate the conducting wires is to use a primary polishing slurry, to polish off both the excess conductor and liner material. The polishing slurry, pad, and operating parameters of the chemical mechanical planarization process are specifically optimized for a high chip yield, at high removal rate of both the conductor and liner. The metal polishing slurry usually consists of alumina particles, from 100 to 500 nm in diameter, in an acidic (1&lt;pH&lt;4) environment, with between 0.1 and 0.6M concentration of oxidizer such-as hydrogen peroxide, ferric nitrate, or potassium iodate. The role of each ingredient has a special function. The oxidizer is added to chemically attack the metal and to enhance the polishing rate. Alumina, which is considerably harder than other abrasives such as silica, ceria, or zirconia, is usually used for a high rate of polishing of the metal and slow rate of polishing of oxide. Finally, the pH is acidic to prevent polishing of the silicon oxide.
There are a number of problems that can occur during the chemical mechanical planarization process which can adversely affect the chip yield. One of the biggest problems is erosion of the dielectric, which is caused by the variation of the pattern densities of conductors across the wafer. In large regions where there is a high concentration of the metal, there is often not enough dielectric to define a polishing plane. As a result, the polishing pad tends to flex and polish the dielectric that is in the region, resulting in a large area of the wafer that is substantially lower than other places on the chip. This non-planarity tends to replicate to the next level of the chip, where it can be filled with metal or cause alignment issues.
Another problem is that the primary slurry described above can cause scratches in the dielectric, which will replicate to further levels. Although scratches are somewhat inevitable in a polishing process,. the severity of these scratches are increasing with the use of lower dielectric constant materials such as organic-based or aero-gel-based dielectrics. To eliminate the effects of severe scratches, the primary polish is usually followed by a second "touch-up" chemical mechanical planarization step that removes between 10 and 100 nm of the dielectric. This step is often accomplished with a silica-based, alkaline slurry that is formulated for a high oxide removal rate. The application of this second planarizing step is not without its own problems. This step often causes erosion of oxide in regions of high pattern density, which is the creation of more topography. In addition, because the touch-up slurry is alkaline, while the primary slurry is acidic, precipitates can form on the wafer when these two slurries contact, creating a problem in cleaning the surface.
Another problem that often occurs during chemical mechanical planarization is residual metal after polishing. Often the residual metal results from topography that exists on the wafer before the deposition of the liner materials. These regions of non-planarity might be caused by erosion or scratches at a previous level, which then replicate up through the deposition of the oxide and are then filled with the metal. Because these defects represent metal that is below the plane to which one is trying to polish, they are virtually impossible to remove via chemical mechanical planarization. That is, chemical mechanical planarization is very poor at removing material that is recessed into the dielectric. As a result, these metal-filled scratches and regions of erosion represent regions of unremoved, excess metal that tends to result in short circuits.
There have been a number of approaches that have been taken to alleviate some of these problems with the chemical mechanical planarization process. U.S. Pat. No. 5,676,587 issued to Landers et al. represents one attempt to improve upon the conventional, two-step process. The disclosed process comprises a two-step Chemical Mechanical Polishing or CMP process for removing a W or Cu layer and an underlying Ti/TiN or Ta/TaN liner, from the surface of an oxide layer, without damaging the oxide layer. In the first step of the process, an alumina-based slurry is used in a conventional CMP process to remove the W or Cu as well as an upper portion of the liner film. The first step is terminated while a substantial portion of the liner fill remains on the oxide layer. The second step uses a neutral-pH, silica-based slurry which is selective to Ti/TiN and Ta/TaN to remove the remainder of the liner film. By stopping the first step well before the polishing platen of the CMP apparatus has reached the oxide layer, the relatively abrasive alumina-based slurry is prevented from damaging the surface of the oxide layer, while the second step selectively removes the liner film.
Like the Landers et al. process, U.S. Pat. No. 5,244,534 issued to Yu et al. also discloses a two-step CMP process. The first CMP step uses a slurry containing abrasive particles, such as Al.sub.2 O.sub.3, and etchants selective to W, such as H.sub.2 O.sub.2 and either KOH or HN.sub.4 OH or other acids and bases. The first CMP step removes the W while removing little of the oxide layer. During the last phase of the first step, which completely removes barriers such as Ti or TiN over the surface of the wafer, a portion of the W below the level of the oxide surface is also removed. Thus, a recessed W plug remains in the oxide layer. This recessed plug is both typical of conventional plug formation and difficult to couple with a subsequent layer of metal or other material.
Therefore, a second CMP step is applied. The second CMP step uses a slurry containing abrasive particles, such as Al.sub.2 O.sub.3, and etchants selective to the oxide material of the dielectric layer, such as a basic mixture of H.sub.2 O and KOH. The second step removes a portion of the oxide layer to a level even with, or slightly below, the level of the W plug.
CMP has some inherent problems that are exacerbated when building extremely small semiconductor structures. As structural dimensions continue to shrink, the size of defects that can be tolerated shrinks as well. Traditionally, semiconductor manufacturers were bothered by conductive residuals shorting damascene features. Such shorts become evident as yield loss or reliability problems. At ever-decreasing structural dimensions, the effect of these residuals has become a major yield problem. Some of the problems inherent in CMP are discussed below; they result in unacceptable yield loss and reliability problems.
First, scratches are inherent to the CMP process because it uses an abrasive slurry. The softer the dielectric, the harder it is to control detrimental scratches. Prospective low-dielectric materials such as aerogels and organic-based materials can be very soft; therefore, the problem will be more pronounced in the future. These scratches can fill with liner or metal material and create shorts in the final structures. As structures get smaller and smaller, this risk becomes more and more of a problem: the distance to cause a short becomes shorter and shorter.
Another problem inherent in CMP processes is that metal material from the via or metal line tends to smear to the next via or metal line. The metal contact causes a short. This problem also becomes worse as structures get smaller and smaller. Photo-etch interaction defects, which cause serration or fluting of the edge of the via or metal line, add to this problem.
The slurries used with CMP processes present still another problem. It is hard to find slurries that polish metals and oxides at the same rateconsequently, CMP creates topography variations. These topography variations are replicated to higher levels of the device structure, where they cause the same problems. The need to provide a substantially planar surface after polishing is critical.
U.S. Pat. No. 5,173,439 issued to Dash et al. combines two CMP process steps with an intermediate reactive ion etching (RIE) step. Because the final polish or etch step is CMP, however, Dash et al. encounter the same problems outlined above for all chemical mechanical planarization processing. Specifically, Dash et al. focus on a process for forming wide, dielectric- or conductor-filled isolation trenches in semiconductor substrates. An etch stop (e.g., silicon nitride) is deposited on the substrate. A layer of dielectric or conductor material (e.g., silicon dioxide) is conformally deposited on the etch stop and in the trench. Then a layer of etch-resistant material (e.g., polysilicon) is deposited.
A first CMP process removes all of the etch-resistant material except that above the wide trench, such that the remaining portions of the etch-resistant material reside within the width of the trench. This first CMP process neither removes the layer of dielectric (or conductor) material nor enters the etch stop. A plug of dielectric (or conductor) material is formed above the trench by RIE of the layer of dielectric (or conductor) material, which is not covered by the etch-resistant material, down to the top of the trench. The RIE reacts with the dielectric (or conductor) material, but not with the etch-resistant material, and is terminated by the etch stop. Finally, a second CMP process removes the plug to obtain a dielectric- or conductor-filled trench having an upper surface in substantial planarity with the upper surface of the substrate.
Dash et al. recognize other conventional techniques used to form planarized wide trenches. Many of these techniques teach masking which, although somewhat effective, has certain drawbacks. Masking techniques require extra masking and photolithographic steps, adding two processing steps and creating problems of alignment. The mask must be perfectly aligned to deposit the photoresist exactly.
The deficiencies of the conventional planarization processes show that a need still exists for an improved process of removing the tungsten or copper layer and a Ti/TiN or Ta/TaN liner film from the surface of an oxide layer. To overcome the shortcomings of the conventional processes, a new planarization process is provided. An object of the present invention is to provide a process for removing a metallization layer and an underlying liner, from the surface of a dielectric layer, without damaging the dielectric layer.
Another object of the present invention is to provide an improved process for planarizing conductor-filled trenches in the surface of a semiconductor substrate. It is another object to provide a self-aligned planarization process. It is yet another object of the present invention to provide a process that does not require expensive and time-consuming photolithographic techniques to planarize a conductor-filled trench. It is a further object to provide a process using etch steps that reduce the process sensitivity to endpoint control and increase process windows. A related object is to provide an improved process of etching back tungsten or copper layers on semiconductor wafers to allow for good contact with layers of metal or other conductive material which are subsequently deposited.